EDN

FPGA-to-ASIC conversion a crucial concern

It is clear that FPGAs are great for prototyping and low-volume production. It's also clear, however, that any relatively complex mid- to high-volume design for which power consumption, component cost ...
Embedded

Moving from FPGA to ASIC for your AI chip? Here’s what you should know

Perhaps you are designing an embedded inference engine for edge computing. Or you are taking the next step in automotive vision processing. Or maybe you have an insight that can challenge Nvidia and ...
AV Network

Justin Kennington on AV Supply Chain Using FPGA vs. ASIC Chips

SDVoE Alliance President, Justin Kennington shares his perspective on how FPGA versus ASIC chips impacts the product supply chain in the AV industry. When you purchase through links on our site, we ...
EDN

FPGAs vs. ASICs

Electronic News sat down with Jeff Jussel, VP of marketing at Celoxica; Babek Hedayati, senior director of product solutions marketing at Xilinx; and Aiden Kelly, manager of ASIC methodology at IBM ...
Digi Times

FPGA vs ASIC: Altera CEO highlights FPGA's advantage in AI era

Embedded World 2025 officially commenced this week in Nuremberg, Germany, with Sandra Rivera, CEO of FPGA company Altera, delivering the keynote address. In her presentation, Rivera discussed key ...
SDxCentral

Intel Agilex FPGA, ASICs Power Next-Gen DPUs

Intel debuted two infrastructure processing units (IPUs) alongside an updated acceleration development platform during its annual Architecture Day this week. Intel first teased the IPUs — what the ...
Digi Times

Lattice confident in FPGA competitiveness against ASIC

US-based FPGA maker Lattice Semiconductor held its annual Developers Conference this week, during which the company announced its latest Nexus 2 platform and expansions to its mid-range Avant platform ...
Electronic Design

Structured ASICs

Heard about Structured ASICs but aren't sure exactly what they are and how to use them. In this edition of REFRESH! EEPN contributing editor, Andrew Leone, gives you a guided tour of these devices and ...
Business Wire

MathWorks Speeds FPGA and ASIC Verification with Universal Verification Methodology (UVM) Support

NATICK, Mass.--(BUSINESS WIRE)--MathWorks today announced that HDL Verifier provides support for the Universal Verification Methodology (UVM) starting with Release 2019b, which is currently available.
BizTech

What Is an FPGA? Understanding Field-Programmable Gate Arrays

Ernie Smith is a former contributor to BizTech, an old-school blogger who specializes in side projects, and a tech history nut who researches vintage operating systems for fun. When it comes to major ...
VentureBeat

FPGA chips are coming on fast in the race to accelerate AI

AI is hungry, hyperscale AI ravenous. Both can devour processing, electricity, algorithms, and programming schedules. As AI models rapidly get larger and more complex (an estimated 10x a year), a ...